1. Field of the Invention
The invention relates to a semiconductor integrated circuit (hereinafter abbreviated as IC) structure and a method for forming the same, and more particularly, to a semiconductor IC structure including negative thermal expansion (hereinafter abbreviated as NTE) material and a method for forming the same.
2. Description of the Prior Art
Semiconductor IC structures are formed from appropriate substrates over which are formed desired semiconductor circuit elements and interconnections that include patterned conductive layers separated by dielectric layers. Also, in the course of manufacturing an IC, dielectric material is formed over the abovementioned resulting structure for purposes of providing electrical isolation and protecting the relatively fragile underlying semiconductor circuit elements.
However, it is found dielectric layers suffer cracking more than conductive layers. And cracking within dielectric layers is often attributable to physical stress onto dielectric layers. In turn, physical stress is often amplified as dimensions of the semiconductor IC structures decrease. Therefore, solution to this dielectric cracking issue is in need.